This is a basically the simplest possible pipelined CPU. It was the final project for my computer architecture class. It is written in VHDL and can be compiled using ghdl. The CPU is Turing complete, but it only recognizes a very small subset of the full MIPS instruction set. It implements the following MIPS instructions:

Arithmetic instructions:

• add - adds two registers
• sub - subtracts two registers
• ori - performs an or on a register and an immediate value
• nor - performs nor on two registers
• sll - shift left logical on a register
• srl - shift right logical on a register
• slt - returns true if one register is less than another

Branching instructions:

• j - jump to the value in the instruction
• jr - jump to a register value
• jal - jump to a value and remember current location
• beq - branch on equal

Memory operations:

• lw - load word from memory
• sw - store word to memory

other instructions:

• halt - stops the CPU

Basic architecture

wikipedia

The code for this project is available on github: http://github.com/jncraton/MIPS-Lite